The present invention relates generally to a PLL (Phase Locked Loop) circuit which outputs an oscillation clock synchronous with a reference clock, and a phase lock detector. More particularly, the present invention relates to a PLL circuit which maintains synchronization of a reference clock with an oscillation clock, and a lock detector which detects that the oscillation clock is synchronous with the reference clock.
In video applications, PLL circuits are used in synchronous reproduction of a color signal according to a burst clock included in a composite video signal. There are two types of PLL circuits: a digital circuit type and an analog circuit type. The digital PLL circuit has a CMOS structure and includes a memory for storing data of the oscillation timing of an oscillation clock, a digital filter and a multiplier. The digital PLL circuit therefore has a relative large circuit area. The analog PLL circuit has a CMOS structure and includes an external component like a capacitor. The analog PLL circuit is thus smaller than its digital counterpart.
FIG. 1 is a block diagram of a conventional analog PLL circuit 100 for use in a television receiver. The PLL circuit 100 includes an exclusive OR (XOR) gate 101, a tristate buffer 102, a charge pump circuit 103 or a CMOS structure, a low-pase filter (LPF) 106, a Voltage controlled oscillator (VCO) 107 and a xc2xc frequency divider 108.
The XOR gate 101 has a first input terminal for receiving a burst clock (reference clock) Rc with a duty ratio of 50%, a second input terminal for receiving an output clock Pc with a duty ratio of 50% output from the xc2xc frequency divider 107, and an output terminal for outputting a clock Si which represents the result of comparison of the phase of the burst clock RC with that of the output clock Pc. FIG. 2 is a timing diagram illustrating the operation of the XOR 101. In a color television of the NTSC (National Television System Committee) system, the burst clock Rc has a frequency of 3.58 MHZ. When the period of the burst clock Rc matches with that of the output clock Pc and when the phase of the output clock Pc in advanced by 90xc2x0 from that of the burst clock Re, the clock 81 which has a frequency double that of the burst clock Rc and a duty ratio of 50% is output (see FIG. 2).
The tristate buffer 102 receives a control signal RE, which is enabled in accordance with the period of the burst clock, and the output clock Si. The tristate buffer 102 sends the output clock S1 to the charge pump circuit 103 when the control signal RE is enabled to have an xe2x80x9cH levelxe2x80x9d and sets the output in a high impedance state when the control signal RE is enabled to have an xe2x80x9cL levelxe2x80x9d.
The charge pump circuit 103 includes a pMOS transistor 104 and an nMOS transistor 105, connected in series between a power supply and ground. The pMOS transistor 104 and nMOS transistor 105 are turned on or off in response to the output clock S1 output by the tristate buffer 102. When the pMOS transistor 104 is on, a current Ip flows into the LPF 100 from the power supply, and when the nMOS transistor 105 is on, a current In flows through the LPF 106 into ground. As the LPF 106 is charged or discharged by the current Ip or In, the LPF 106 smoothes the clock S1 and outputs a control voltage Vt to the VCO 107. The VCO 107 supplies an oscillation clock Fv having a frequency according to the voltage value of the control voltage Vt to the xc2xc frequency divider 108. In the case of television, the oscillation clock Fv has a frequency of 14.31818 MHZ, four times as high as the frequency of the burst clock Rc. The xc2xc frequency divider 108 sends the clock Pc, obtained by frequency-dividing the oscillation clock Fv by four, to the XOR gate 101.
An A/D converter 109 receives the oscillation clock Fv from the VCO 107, and performs analog-to-digital conversion to generate a digital signal S2 by sampling a composite video signal CV according to the oscillation clock Fv. The composite video signal CV includes a color signal which is extracted by the AID converter 109.
The frequency of the oscillation clock Fv output from the VCO 107 varies due to external factors such as a temperature change and a change in power supply potential. To suppress a change in the frequency of the oscillation clock Fv or to obtain the oscillation clock Fv of a constant frequency from the VCO 107, the control voltage Vt should be adjusted in accordance with such external factors. One way of controlling the control voltage Vt is to change the duty ratio of the output clock S1 of the XOR gate 101. This is because the control voltage Vt is output as the LPF 106 is charged or discharged by the operation of the charge pump circuit 103, according to the duty ratio of the output clock S1.
Suppose that the control voltage Vt which is one-half the power supply potential is acquired when an ideal clock S1 with a duty ratio of 50% is output, as shown in FIG. 3B. To set the control voltage Vt larger than one-half the power supply potential, as shown in FIG. 3A, it is necessary to output the clock S1 whose duty ratio is greater than 50%. To set the control voltage Vt smaller than one-half the power supply potential, as shown in FIG. 3C, the clock S1 whose duty ratio is smaller than 50% should be output. In the cases of FIGS. 3A and 3C, since the difference between the phase of the burst clock Rc and the phase of the clock Pc is not 90xc2x0 , the phase of the oscillation clock Fv is shifted from the desired phase.Sampling of a video signal according to the oscillation clock Fv with the shifted phase makes it difficult to accurately reproduce a color signal, resulting in a change in color.
In the television receiver, various signal processes are executed using the oscillation clock Fv from the PLL circuit 100. When the oscillation clock Fv is shifted at the time the receiver is powered on or the channel is changed, various signal processes may not be carried out properly. It is therefore desirable to detect if the oscillation clock Fv keeps a predetermined phase.
It is a primary objective of the present invention to provide a PLL circuit which maintains an oscillation clock synchronous with a reference clock.
It is a secondary objective of the present invention to provide a lock detector which detects that the oscillation clock is synchronous with the reference clock.
Briefly stated, the present invention provides a phase locked loop (PLL) circuit for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock. The PLL circuit includes: a voltage controlled oscillator receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage; a comparison circuit receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result; a charge pump circuit, connected to the comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the charge pump pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential; and a low-pass filter, connected between the charge pump circuit and the voltage controlled oscillator, for smoothing the output of the charge pump circuit to produce the control voltage. The charge pump circuit includes: first and second transistors which are alternately turned on and off in response to the comparison signal; a constant current source for supplying a constant current; a first current mirror circuit, connected between the first transistor and the output terminal of the charge pump circuit, for allowing flow of a constant drive current according to the constant current or the constant current source when the first transistor is turned on; and a second current mirror circuit, connected between the second transistor and the output terminal of the charge pump circuit, for allowing flow of a constant drive current according to the constant current of the constant current source when the second transistor is turned on.
The present invention further provides a phase locked loop (PLL) circuit for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock, The PLL circuit includes: a voltage controlled oscillator receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage; a comparison circuit receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result; a first charge pump circuit, connected to the comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the first charge pump circuit pulls a constant current to ground from an output terminal of the first charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the first charge pump circuit when the power supply potential is selected, thereby producing a first output which alternately repeats the ground potential and the power supply potential; a second charge pump circuit, connected to the comparison circuit, a ground potential and a power supply potential and having a drive performance with a higher output load than the first charge pump circuit, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the second charge pump circuit pulls a constant current to ground from an output terminal of the second charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the second charge pump circuit when the power supply potential is selected, thereby producing a second output which alternately repeats the ground potential and the power supply potential; a low-pass filter, connected between the first and second charge pump circuits and the voltage controlled oscillator, for smoothing one of the first and second outputs of the first and second charge pump circuits to produce the control voltage; a lock detector receiving the reference clock and the oscillation clock, detecting if the oscillation clock maintains a substantially constant phase difference with respect to the phase of the reference clock and producing a detection signal indicative of a detection result; and a selecting circuit, connected to the first and second charge pump circuits and responsive to the detection signal, for operating the first charge pump circuit when the oscillation clock maintains the substantially constant phase difference with respect to the phase of the reference clock and operating the second charge Pump circuit when the oscillation clock does not maintain the substantially constant phase difference with respect to the phase of the reference clock.
The present invention provides a phase locked loop (PLL) circuit for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock. The PLL circuit includes: a voltage controlled oscillator receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage; a comparison circuit receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result; a charge pump circuit, connected to the comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the charge pump circuit pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential i selected, thereby producing an output which alternately repeats the ground potential and the power supply potential; a low-pass filter, connected between the charge pump circuit and the voltage controlled oscillator, for smoothing the output of the charge pump circuit to produce the control voltage; a lock detector for receiving the reference clock and the oscillation clock, detecting if the oscillation clock maintains a substantially constant phase difference with respect to the phase of the reference clock and producing a signal indicative of a detection result; and a switch, connected to one of the input and output of the low-pass filter and responsive to the signal indicative of the detection result from the lock detector, the switch operating to supply one of the ground potential and the power supply potential to one of the input and output of the low-pass filter when the oscillation clock does not maintain a substantially constant phase difference with respect to the phase of the reference clock for at least a predetermined time.
The present invention further provides a lock detector for use in a phase locked loop circuit and for detecting if an oscillation clock maintains a substantially constant phase difference with respect to a phase of a reference clock, the oscillation clock having a frequency n (n: a natural number) times that of the reference clock, a first clock, obtained by dividing the frequency of the oscillation clock by n, supplied to the lock detector. The lock detector includes: a phase shifter for shifting a phase of the first clock by the substantially constant phase difference to produce a second clock; an exclusive OR gate, connected to the phase shifter, for receiving the reference clock and the second clock, and for producing an arithmetic operation output signal having a duty ratio; a low-pass filter for receiving and smoothing the arithmetic operation output signal to produce an output voltage according to the duty ratio of the arithmetic operation output signal; and a determining circuit, connected to the low-pass filter, for comparing the output voltage with a predetermined reference voltage and determining a locked state of the oscillation clock based on a comparison result.
The present invention provides an image signal processing apparatus for producing chrominance information and luminance information from a composite video signal containing a sync component, a luminance component and a chrominance component, The image signal processing apparatus includes: a sync signal detector for acquiring a horizontal sync signal indicative of a timing for a horizontal scan, from the sync component contained in the composite video signal; an burst extracting;circuit for extracting a burst clock indicative of a phase of the chrominance component, from the composite video signal; a Y/C separator for separating the luminance component and the chrominance component from the composite video signal; a phase locked loop circuit, connected to the/burst extracting circuit, for receiving the burst clock as a reference clock and producing an oscillation clock having a frequency n (n: a natural number) times that of the burst clock and maintaining a substantially constant phase difference with respect to a phase of the burst clock; a reproducing circuit, connected to the Y/C separator and the phase locked loop circuit, for receiving the luminance component and the chrominance component in accordance with the oscillation clock and reproducing the luminance information and the chrominance information; a frequency divider, connected to the phase locked loop circuit. for frequency-dividing the oscillation clock by n to produce a frequency-divided clock; and a lock detector, connected to the frequency divider and the burst extracting circuit, for receiving the burst clock and the frequency-divided clock and detecting a locked state of the phase locked loop circuit based on a phase difference between the burst clock and the frequency-divided clock. The lock detector includes; a phase shifter for shitting a phase of the frequency-divided clock by the constant phase difference to produce a phase shift clock: a logic gate. connected to the phase shifter, for receiving the reference clock and the phase shift clock and producing an arithmetic operation output signal having a certain duty ratio; a low-pass filter for receiving and smoothing the arithmetic operation output signal to produce an output voltage according to the duty ratio of the arithmetic operation output signal; and a determining circuit, connected to the low-pass filter, for comparing the output voltage with a predetermined reference voltage and supplying a reset signal to the phase locked loop circuit when the output voltage exceeds the predetermined reference voltage,